Flood

UART DMA Back to Back Packets Debug

Symptom

Spaced packets get the right response. Packets arriving back to back lose one or garble it. The registers and bit fields are on the Datasheet tab.

Circuit

Block diagram: packets arrive on USART1 RX, the firmware formats a response into the RAM buffer tx_buf, DMA2 Stream 7 reads that buffer into the USART1 data register, and PA9 carries the response to the host serial console with a TP1 capture on the net

Pass condition

Each four-byte packet must produce its own response line, RX:<b0>,<b1>,<b2>,<b3>, in decimal.

Expected output: eight bytes A B C D P Q R S arrive back to back as two four-byte packets, and the capture holds two response lines, RX:65,66,67,68 from the first packet and RX:80,81,82,83 from the second

Notes

The upstream link sends two packets and the program answers both. On this bench only DMA2 needs its clock enabled, and the program enables it.

Related challenges

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