Behind Schedule

FreeRTOS Missed Deadline Debug

Symptom

Every boot, the log reads report: late by 13 ms. The report task must have the sample buffer by 120 ms after boot.

Circuit

Bench wiring: U1, an STM32F4 running FreeRTOS, runs three tasks. acquire, priority 1, starts at once and refreshes the sample buffer in about 110 ms; report, priority 3, starts at 10 ms, reads the sample buffer and is due by 120 ms after boot; radio, priority 2, starts at 20 ms and builds the telemetry frame in about 21 ms. PA9 carries USART1 TX to J1, a serial console

Pass condition

The log reads report: on time.

Expected log on the serial console: one line, report colon on time, printed once the report task has the sample buffer by 120 ms after boot

Notes

FreeRTOS V11.1.0, preemptive, 1 ms tick. Nothing outside the board drives the tasks, so every boot runs the same timeline.

Related challenges

Loading the interactive arena.